Chee, Hock Leong
(2023)
Non-volatile FPGA architecture based on Resistive Random-Access Memory.
PhD thesis, University of Nottingham.
Abstract
The advent of massive-scale data-intensive applications from Internet-of-Things (IoT), Artificial Intelligence (AI), neural networks, cloud computing and its services, machine learning, and 21st century modern technology adoption coupled with the increasing environmental awareness of modern society has led to the demand for more digital devices with higher computing power and increased energy consumption efficiency. One of the widely used computing device is the Field-Programmable-Gate-Array (FPGA).
This PhD research aims to develop a nonvolatile FPGA (nvFPGA) as an evolution of the conventional complementary-metal-oxide-semiconductor (CMOS)-based volatile FPGAs. To achieve this, nonvolatility (NV) is implemented through the use of next-generation emerging memory devices called Resistive Random-Access Memories (ReRAMs).
An analysis of the conduction mechanisms behind multi-filamentary ReRAMs is first performed and a model based on oxygen vacancy (VO) migration and trap-assisted tunnelling (TAT) is developed. The model successfully demonstrates the contribution of each individual filament in the ReRAM’s metal-oxide layer to the resistive switching (RS) behaviour. In addition to that, the model also shows that the barrier height between the conductive filaments (CFs) in the metal-oxide and the electrode is a strong factor in the CF formation/rupture process. The multi-filamentary switching ReRAM also enables multi-bit (MB) switching; increasing the number of bits that can be stored in the ReRAM cell. The model matches well with experimental results with the largest difference seen in the first intermediate resistive state (IRS) at 30.35%. Compared to the single-filament ReRAM model, the current level of the multi-filamentary ReRAM is 190% higher due to the extra conduction paths through the additional filaments.
NV is then implemented in two fundamental FPGA elements; the configurable logic block (CLB) which is responsible for the FPGA combinatorial logic and the switch block (SB) which is responsible for the FPGA routing configuration.
Inside the CLB are two important components, the lookup table (LUT) and the D flip-flop (DFF). An analysis of a single-bit NV LUT (SB-nvLUT) array and its controller is first performed and the SB-nvLUT successfully eliminates the sneak path problem that is common in ReRAM arrays. A voltage-mode sense-amplifier is then developed to raise the output voltages of the ReRAMs in the array from subthreshold voltages to voltage levels that are detectable to a differential comparator. The voltage-mode sense-amplifier utilizes 20% lower transmission gates compared to conventional ReRAM sense-amplifier designs and shows 32% and 54% improvements in READ time and energy dissipation compared to an existing voltage-mode design and 85% and 59% improvements in the same respective metrices compared to an existing current-mode design.
The MB NV LUT (MB-nvLUT) and its controller is then developed with 2-bit ReRAMs in the LUT array. The MB-nvLUT reduces the array size by 0.5x and the number of controller gates by 0.25x compared to the SB-nvLUT. Compared to the SB-nvLUT, the MB-nvLUT has an average of 2x lower delay, 1.22x lower energy consumption, and 2.46x lower energy delay product (EDP) for WRITE 0; 2x lower delay, 2x lower energy consumption, and 4.6x lower EDP for WRITE 1; 2x lower delay, 1x lower energy consumption, and 2x lower EDP for WRITE 0110; 9.2x lower delay, 128x lower energy consumption, and 153x lower EDP.
Two NV electronic storage elements are developed alongside the NV DFF (nvDFF) which are the NV D latch (nvD latch) and the NV dynamic random-access memory (nvDRAM). Measurements of performance metrices such as Clk-to-Q delay, Q rise time/Q_b fall time, Q fall time/Q_b rise time, power dissipation, and WRITE0 and WRITE1 delay and power dissipations are performed. The NV storage elements demonstrate successful data retention during power disruption events, providing advantage over their CMOS-based counterparts; the nvDRAM does not require an energy consuming refresh operation compared to the CMOS-based DRAM and the nvD latch and nvDFF allows proper SLEEP modes and stores data in the event of power disruption. Although introduction of NV incurs a drawback in the aforementioned performance metrices, the NV designs nevertheless demonstrate comparable power consumptions and delay timings when compared to conventional electronic designs.
The nvFPGA made up of an nvCLB (comprising the MB-nvLUT and the nvDFF) and an nvSB (replacing the SRAM storage elements with the nvDRAM) is then presented. The NV properties of the nvCLB is demonstrated together with performance metrices such as the delay timing, energy dissipation, and EDP. The average WRITE delay and EDP of the nvLUT are respectively 73.463% and 99.79% higher than the SRAM LUT while the READ delay and EDP of the nvLUT are respectively 97.295% and 91.184% lower than the SRAM LUT. The improvements in READ performance metrices is advantageous for FPGA applications which typically have numerous READ operations after a single WRITE. The nvDFF implements NV with increase of 5.089% and 61.1045% respectively in the average delay and EDP. The average WRITE delay and EDP of the nvSwB are 12253.17 ps and 7.588 ps nJ respectively while the average READ delay and EDP of the the nvSwB are 200 ps and 3.814x10-2 ps nJ respectively. Although the nvSwB performance metrices are higher than SRAM-based SwBs, the nvSwB values are in picoseconds and are capable of operating at conventional high frequencies.
| Item Type: |
Thesis (University of Nottingham only)
(PhD)
|
| Supervisors: |
Kumar, T. Nandha
Al-Murib, Haider Abbas Mohammed |
| Keywords: |
D Flip-Flop, D Latch, DRAM, FPGA, LUT, memory, multi-bit, non-volatile memory, resistive memory, RRAM |
| Subjects: |
T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Faculties/Schools: |
University of Nottingham, Malaysia > Faculty of Science and Engineering — Engineering > Department of Electrical and Electronic Engineering |
| Item ID: |
72313 |
| Depositing User: |
Chee, Hock
|
| Date Deposited: |
18 Feb 2023 04:40 |
| Last Modified: |
01 Mar 2024 04:30 |
| URI: |
https://eprints.nottingham.ac.uk/id/eprint/72313 |
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