Co-design/simulation of flip-chip assembly for high voltage IGBT packages

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Rajaguru, P., Bailey, Christopher, Aliyu, Attahir Murtala, Castellazzi, Alberto, Pathirana, V., Udugampola, N., Trajkovic, T., Udrea, F., Mitchelson, P.D. and Elliot, A.D.T. (2017) Co-design/simulation of flip-chip assembly for high voltage IGBT packages. In: 23rd International Workshop on Thermal Investigations of ICs and Systems, THERMINIC 2017, 27-29 September 2018, Amsterdam, Netherlands.

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Official URL: https://ieeexplore.ieee.org/document/8233847/

Abstract

This paper details a co-design and modelling methodology to optimise the flip-chip assembly parameters so that the overall package and system meets performance and reliability specifications for LED lighting applications. A co-design methodology is employed between device level modelling and package level modelling in order enhance the flow of information. As part of this methodology, coupled electrical, thermal and mechniacal predictions are made in order to mitigate underfill dielectric breakdown failure and solder interconnect fatigue failure. Five commercial underfills were selected for investigating the trade-off in materials properties that mitigate underfill electrical breakdown and solder joint fatigue.

Item Type:	Conference or Workshop Item (Paper)
RIS ID:	https://nottingham-repository.worktribe.com/output/884676
Additional Information:	doi:10.1109/THERMINIC.2017.8233847
Schools/Departments:	University of Nottingham, UK > Faculty of Engineering > Department of Electrical and Electronic Engineering
Depositing User:	Burns, Rebecca
Date Deposited:	10 May 2018 14:32
Last Modified:	04 May 2020 19:08
URI:	https://eprints.nottingham.ac.uk/id/eprint/51686

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