Influence of gate bias on the avalanche ruggedness of SiC power MOSFETs

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Fayyaz, Asad, Castellazzi, Alberto, Romano, G., Riccio, M., Urresti, J. and Wright, N. (2017) Influence of gate bias on the avalanche ruggedness of SiC power MOSFETs. In: 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), 28 May-1 June 2017, Sapporo, Japan.

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Abstract

This paper investigates the effect of negative gate bias voltage (VGS) on the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs. The device’s ability to withstand energy dissipation during avalanche regime is a connoting figure of merit for all applications requiring load dumping and/or benefiting from snubber-less converter design. The superior material properties of SiC material means that SiC MOSFETs even at 1200V exhibit significant intrinsic avalanche robustness.

Item Type: Conference or Workshop Item (Paper)
RIS ID: https://nottingham-repository.worktribe.com/output/862170
Additional Information: doi:10.23919/ISPSD.2017.7988986
Keywords: avalanche ruggeddness; silicon carbide; unclamped inductive swithching; power MOSFET; robustness
Schools/Departments: University of Nottingham, UK > Faculty of Engineering > Department of Electrical and Electronic Engineering
Depositing User: Burns, Rebecca
Date Deposited: 27 Feb 2018 12:14
Last Modified: 04 May 2020 18:47
URI: https://eprints.nottingham.ac.uk/id/eprint/50048

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