M, Arya Lekshmi
(2022)
Modelling, fabrication, and characterization of memristor for mitigating the sneak path current in a nano-crossbar memory array.
PhD thesis, University of Nottingham Malaysia.
Abstract
The semiconductor industry looks ahead to Resistive random-access memory (RRAM), (alternatively known as memristor), a promising emerging non-volatile memory technology that can be developed to become a solution for high-density data storage problems. However, the formation of crossbar arrays with RRAM devices results in the origin of leakage current from the unselected cells known as sneak path current, which is identified as the major hindrance to the development of RRAM as it adversely affects data integrity. Among various prevailing solutions to mitigate sneak path current, the effective methods are incorporating a selector switch in association with the memory device to form one selector-one resistor (1S1R) configuration and complementary switching (CRS) devices formed by back-to-back connected RRAMs.
Even though the experimental results of several one selector -one resistor (1S1R) are reported, physical/electrical mechanisms explaining the working of such device integrations are missing; hence the first part of this research work focuses on the analytical/electrical model of a selector device and selector -RRAM integrated device (1S1R) architecture to demonstrate the working of devices and to illustrate how effective is a selector switch in mitigating the sneak path current. The selector device chosen to model is a tri-layer Pt/Ta2O5/TaOx/TiO2/Pt stack with nonlinear characteristics. The model is developed with the concept of electron tunneling across the nanoscale multilayer stack, derived using energy band theory. The current conduction in the proposed selector model is devised with the electric field-driven tunneling mechanisms that co-exist in thin multi-layer devices such as Fowler Northeim tunneling and direct tunneling/hopping. From the simulated selector characteristics, it has been noticed that below the threshold voltage (~0.7 V), the model shows low leakage current attributing to the open switch, while at an input voltage >1.2 V, the current profile exponentially increases attributes to closed switch behavior. The resulting I-V characteristics of the selector model can reproduce desired selector properties such as high non-linearity (∼1600), high selectivity (∼104 ), high current density (∼107 A/cm2 ), and low OFF-current (∼46 nA) in agreement with the measured device characteristics.
In addition, the proposed selector model is integrated with established RRAM models such as HP memristor, Pt/Ta2O5/TaOx/Pt RRAM (SAMSUNG), TiN/TiOx/ HfO2/Pt (Stanford-PKU) model, and generalized RRAM device models proposed by Yakopcic to demonstrate the reduction in sneak path current achieved. Among these models, the proposed selector withTiN/TiOx/HfO2/TiN model reduced 99.8 % of the sneak current at low dimensional arrays, whereas the reduction in sneak current with HP memristor and Pt/Ta2O5/TaOx/Pt model are 96% and 98% respectively. Moreover, it is noticed that V/3 based scheme is more suitable for performing read/write in a nano-crossbar array among various writing schemes.
Several RRAM and selector model parameters are inherited to the 1S1R model, thus enabling it to reduce sneak path current. For instance, the nonlinear selector characteristics are directly reflected on the 1S1R curves, ensuring the reduction in sneak path current. The nonlinearity of Ta2O5/TaOx, TiOx/HfOx, TiOx/TiOx-2 are ~2, ~5, and ~5, respectively, while their corresponding 1S1R models exhibited 50, 20, and 55, respectively. Similarly, the Roff/ Ron ratio of RRAM is directly absorbed to 1S1R. Further, the Roff/Ron ratios obtained with 1S1R configuration of Ta2O5/TaOx, TiOx/HfOx, TiOx/TiOx-2 are ~400,~100, and 15, respectively. Likewise, another parameter that determines the sneak current reduction is off-current in 1S1R. Low OFF-current is another desirable factor to eliminate the sneak current. The selector- Ta2O5/TaOx combination provided off-current as low as 0.04 μA whereas 1S1R with Stanford PKU model is 8 nA and 1S-HP memristor combination is 0.01 μA. In addition, the optimum input voltage required to assert on selected/ unselected crossbar array lines to attain SET and RESET voltages are predicted. In Pt/Ta2O5/TaOx/TiO2/Pt selector- Pt/Ta2O5/TaOx/Pt RRAM integrated circuit, SET/RESET voltage is falling within ~2.7-3.6 V/>=~4.4 V whereas in HP and Stanford model these readings are approximately 3.5/-3.7 V and 2.5/-3.0 V respectively.
While in Pt/Ta2O5/TaOx/Pt device model, it has been observed that its experimental I-V characteristics show an increase in current level beyond RESET voltage. However, it has not been addressed in the existing analytical/ electrical models. Hence, an analytical and electrical model has been proposed to incorporate the increased current conduction by considering an additional state-independent current component that flows through the area outside the conduction filament(OCF). The current component is modeled by the trap assisted tunneling (TAT) mechanism, where the oxygen vacancy traps present at OCF enable the electrons to tunnel through that area. Moreover, the variability in the Pt/Ta2O5/TaOx/Pt device characteristics over multiple cycles of input is also explained and simulated by considering three possible factors such as multifilament formation in the device, variation in the radius of the conduction filament(CF), and variations in tunneling barrier height.Next, a comparison of the sneak path current reduction in the 1S1R array and CRS array is carried out, where CRS reduced 93% of the total sneak path current compared to 1S1R. Analysis shows that 1S1R outperforms the CRS model (back-to-back connected RRAM) configuration. The major challenges noticed with the configuration of 1S1R are the shared electrode, compatibility of current /voltages of the chosen selector, and RRAM device. Similarly, the drawbacks identified with CRS devices formed with back-to-back connected RRAM devices are; the presence of the shared electrode at the middle of switching layers, related complicated process flow, and interface issues due to multiple metal-semiconductor junctions.
Therefore, a novel bilayer stack fabrication with CRS functionality is proposed in the second part of the research. The proposed CRS stack is implemented with two switching layers (bilayer) thus, eliminating the need for a shared electrode. In the CRS design, atomic layer deposition (ALD) and thermal evaporation methods are exploited to deposit the switching and electrode layers, respectively. The proposed CRS stack has Au/ZnO/Al2O3/FTO structure, and its characteristics are analyzed to validate the complementary switching. The stable CRS state of the device exhibits a high current of ~500 μA during the ON-state and a low current of 300 nA during OFF-state at low input voltages ranging from -0.5 V to 0.5 V, which enables the proposed device to use in crossbar array to mitigate the sneak path current. The device performance to write and read processes is evaluated with pulses of magnitudes ~|2.5| V and 1.3 V, respectively, and a ~ 60μA difference in read-out current between data bits 0 and 1 is noticed. Also, the power dissipation was in the range of microwatts enabling the device to use in medium power applications. The CRS switching in the proposed device is reported to be due to redistribution of oxygen vacancies spanning in both ZnO and Al2O3 layers based on the electric field distribution. In addition to this, the major current transport mechanism in the proposed device is identified as the space charge limited conduction (SCLC).
Analysis shows that self-rectifying memristor with Au/Al2O3/FTO (MIM) structure is the most promising device used in crossbar array to mitigate the sneak path current. In addition, a recently trending self-rectifying RRAM device is fabricated with Au/Al2O3/FTO, metal-insulator-metal (MIM) structure which gives a 1D1R kind of characteristics with the rectification ratio of 200, is a promising value for reducing sneak current. Moreover, the device has shown a specific characteristic of non-zero cross-over phenomenon reported due to the asymmetric MIM structure's capacitive nature. Also, it is reported that the device can be biased appropriately to obtain analog or digital characteristics.Furthermore, a conductive bridge RRAM (CBRAM) and a resistive random-access memory (RRAM) device are developed to study their performance with a selector device(1S1R). The CBRAM is created from Al2O3/ZnO/FTO stacking with Ag top electrode, which shows the multilevel capability enabling the device to be used in high-density memory applications. The novel multilevel device has shown five distinct states achieved with voltage levels that differ at least ∼0.7 V between them. Among five distinct memory states, three resistive states are attained with RESET voltages, and two are attained with SET voltages. The distinguishable resistive levels obtained with RESET voltages 2.3, 3.0, and 3.8 V are 1300, 2700, and 4320 Ω, respectively, whereas two stable resistive levels attained with SET voltages 0.8 and 1.70 V are 3000 and 100 Ω, respectively.
Moreover, the proposed device excels in its Roff/Ron ratio of 354 obtained with HRS/LRS and the ratio of intermediate states IRS1, IRS2, IRS3 to HRS becomes 15, 04 and 27, respectively. The multilevel property of the device is explained after the formation and rupture of multiple metallic filaments. Finally, the cycle-to-cycle and device-to-device variability in device characteristics and statistical distribution of their resistance levels are also analyzed. Then the device is hypothetically connected with Pt/Ta2O5/TaOx/TiO2/Pt selector to obtain 1S1R architecture with multilevel functionality, which gives a Roff/Ron ratio of 102 and the non-linearity of ~25, as well as off-current in the order of nano Amperes enable it to use in crossbar array along with selector.
For conducting a theoretical study with the selector device (1S1R), a RRAM device is also fabricated with Au/Al2O3/ZnO/FTO stack, which shows bipolar resistive switching behavior with excellent retention and endurance(>103)and has offered Roff/Ron ratio of ~200. In contrast, the hypothetical 1S1R configuration of the RRAM device gives a Roff/Ron ratio of 104. Similarly, the non-linearity obtained from combined architecture (hypothetical) is ~100. Moreover, the off-currents observed in both multilevel-CBRAM and RRAM are negligibly low in the range of nano Amperes. All these values indicate the efficiency of the devices to be used in crossbar arrays to mitigate sneak path current.
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