Soft-Start Procedure for a Three-Stage Smart Transformer Based on Dual-Active Bridge and Cascaded H-Bridge Converters

Power electronics based three-stage smart transformers (STs) can be seriously damaged by inrush currents and overvoltages during the start-up phase if the control of the stages is not correctly coordinated. Hence, it is crucial to design properly the start-up procedure, especially in case of modular architectures with distributed dc-links. The design of the start-up procedure depends on the ST power stages topologies, their control systems, and the operation modes. This article proposes a soft-shift start modulation technique that allows to limit the inrush current in the dc/dc isolation stage during the dc-link capacitors precharging. A fast voltage-balancing control, performed by the dc/dc isolation stage, is introduced to avoid overvoltages and unbalanced voltage conditions among the different power cells. Under the proposed method, fast control dynamics is guaranteed thanks to the high frequency bandwidth of the dc/dc isolation stage converters. Theoretical analysis, based on a detailed small signal model of the ST, and simulations are used to demonstrate the principle of the operation. Experimental results, carried out in an ST prototype, confirm the performances of proposed solution in realizing a smooth start-up without voltage/current overshoots.

implemented on the basis of a solid-state transformer or on the basis of a back-to-back converter plus a standard transformer. In the framework of smart grids, the ST concept has recently attracted the attention of industry for the capability to regulate the voltage, the frequency, the active and reactive power flow, and to allow meshed operations of distributed feeders [1]- [6]. Considering the modular three-stage ST based on the cascaded H-bridge (CHB) converter and the dual-active bridge (DAB) converters in Fig. 1, this article focuses on the start-up procedure, which has to be coordinated with the specific control system.
Examining previous literature about STs based on CHB and DAB converters, the design results in multiple control objectives, whereby the medium voltage (MV) dc-link voltages of the power conversion cells can be balanced either by the ac/dc stage control [7]- [9] or by the dc/dc power conversion stage [10]- [12].
In case where the MV-side ac/dc converter is in charge of the MV dc-link voltage balancing control, it allows to employ conventional control strategies already developed for the CHB converter standalone applications. Differently, in [10] and [11], it is demonstrated that the MV dc-link voltage balancing operated by the dc/dc power conversion stage provides improved dynamic performances. In this article, it is proven that the MV dc-link voltage balancing technique presented in [10] is particularly advantageous in order to optimize the start-up operation of modular three-stage STs.
Few studies have been previously addressed on the start-up procedure of the ST. In [13], a preliminary start-up procedure is presented considering a nonmodular ST configuration, but it has to be highlighted that the start-up procedure depends on the ST architecture, the operation modes, such as grid feeding and grid forming, and the control systems. The first studies related to the start-up of modular three-stage STs, and based on a stage-bystage procedure, are proposed in [14]- [16]. In all these cases, conventional control structures are adopted.
Recent studies, such as in [17] and [18], tackle the start-up procedure by focusing on the energization issue based on the use of auxiliary power units (APUs). In all these studies, parameter and/or voltage imbalance conditions during the start-up procedure are not considered and, in conclusion, it is recognized that the fundamental task in the start-up procedure is operated by the ac/dc power stage more than the dc/dc power stage. More recent studies are focused on the role of the dc/dc power stage; in particular, considering a traction three-stage power electronic transformer based on CHB and DAB converters, in [19], a voltage-balance-based control applied to the DAB converters is proposed under parametric/voltage unbalanced conditions. Nevertheless, the system does not provide inrush current control of each single DAB converter and inrush stress-current sharing between different DABs.
Differently, in [20], a combination of model predictive control with current stress optimization scheme allows to achieve high dynamics performance in the output voltage regulation together with self-power balancing of the output parallel DAB converters. The control scheme could support the ST start-up procedure, but start-up issues are not treated in this article.
Considering the same ST topology, in [12], DAB converters are in charge of the low-voltage (LV) dc bus voltage control, the power balance, and the MV dc-links voltage control. Nevertheless, neither details about the design of the control system nor results in case of voltage or power imbalances are provided in this article. Besides, parameter mismatches are not considered in [12].
In [21], the inrush current issue deriving from the transition in case of a power module failure is analyzed. The low-voltage dc-link of the redundant power module is charged by a dedicated charging controller providing constant current to the power module. The focus is on redundancy achievement and not start-up operation. The control method used in [21] cannot be directly extended to the start-up procedure of an ST avoiding modifications.
Finally, in [22], the start-up of some DAB converters connected to a PV source is tackled. The proposed topology is not an ST but a two-stage architecture, which is energized by the LV dc side and not by the MV ac side. Besides, in [22], conventional controllers are adopted, no details about the design procedure are provided and dynamics issues are not tackled.
Considering the configuration in Fig. 1, this article proposes a start-up procedure for a modular three-stage ST energized from the MV ac side. The pivotal role is performed by the dc/dc power conversion stage, which is in charge of the voltage balancing among the MV dc-links and of the inrush overcurrent limitation in the high-frequency transformers (HFTs). A soft-start procedure, based on a modified modulation technique of the DAB converters, provides the aforementioned HFT overcurrent limitations. The main focus is on the first two stages of the ST since, as in [10], the proposed architecture is conceived to be coupled with dc smart grids. The soft-start procedure avoids the use of any APU and it is tailored considering the overall control system. The control system is based on the theoretical model of the ST taking into account voltages imbalance conditions. The rest of this article is organized as follows. In Section II, the main ST start-up and control issues are discussed. Section III deals with the mathematical model of the ST and the balance control design. Section IV describes the soft-start procedure. Section V presents the experimental results. Finally, Section VI concludes this article.

II. ST START-UP AND CONTROL ISSUES
ST start-up implies a soft-start procedure where the following two important conditions need to be satisfied: 1) balancing of the dc-link voltages in the MV side; 2) soft-charging of the capacitors in the LV side. However, it should be considered that due to the mismatch of MV dc-link capacitors parameters, voltage imbalance problems cannot be avoided. If a voltage balance control is not adopted, the deviation of the voltages (and/or currents) may become larger than the insulated gate bipolar transistor (IGBT) blocking voltage limit, and finally, it may results in the failure of the IGBTs and/or of the dc-link capacitors. Therefore, it is very important to balance the voltage in the ST dc-links in transient operation such as the start-up procedure as well as in steady state.

A. Balancing of the DC-Link Voltages in the MV Side
In the literature, there are many kinds of voltage balancing strategies, but they can be essentially classified into following two categories [19].
1) The CHB and the DABs are controlled independently; this means that the voltage balance control in MV is demanded from the CHB stage while the DAB converters control the output voltage in the LV side [23]. 2) The ST is controlled as a single converter. Hence, the MV balancing control is demanded from the DABs together with the voltage control in LV side. A power balance control approach can be adopted by the CHB, to level out the stress in each cell [11] and [24]. The first voltage balancing strategy is the most used [9], but it usually presents a slower dynamic response due to the low switching frequency at which the CHB is normally operated. Furthermore, the CHB control may require modifications to ensure the balancing in all conditions, whereas the DAB solution can freely route the power through the LV dc-link.
The traditional start-up procedure matches with the first ST control approach. It operates the voltage balance in the CHB converter, which starts as first, followed by the DAB converters. Using this procedure, overvoltage and capacitors or IGBTs failures can occur since the CHB control performance depends on the initial conditions of each cell, as discussed in [25] and [26]. In particular, due to the mismatch of the MV resistance and capacitance parameters, the steady-state voltages reached by each dc-link of the CHB in grid-connected passive rectifier operation are quite different among them. Hence, the initial state in each dc-link is different from the others and the voltage balancing cannot be achieved before the CHB converter starts. In such nonlinear systems, the behavior of the controlled variables during the start-up depends on its own values in the initial condition [25], [26]. Usually the control design workflow for the CHB converter is realized considering a linearized model of the control in the steady-state conditions but, in case of a wide voltage range of operation, such a linearized model does not represent the real dynamics anymore, as it happens during the soft-start. Different initial conditions, such as unbalanced dclink voltages, could give rise to unpredictable voltages behavior and it can lead to unstable operation.
Referring to the power stage parameters of a five-level CHB converter, as reported in Table I, and considering the classical CHB-stage voltage balancing approach as in [9], an example is provided in Fig. 2 in case linear PI controllers adjust the CHB cells voltage. The results are related to different initial voltage conditions and it can be observed that the CHB balancing, in the start-up procedure, can bring the system to a stable [see Fig. 2(a)] or unstable [see Fig. 2(b)] operation if the dc-link voltages are initially balanced or unbalanced. In Fig. 2(a), the overall MV dc-link voltage control and the balancing control are turned ON at t = 3 s while a 10% capacitor parameter mismatch occurs at t = 6 s; in this case, satisfactory performance is verified. In Fig. 2(b), a 10% capacitor parameter mismatch is considered as initial condition involving unbalanced MV dc-link voltages.
As a consequence, the same start-up procedure leads the system into unstable condition.
Superior ST start-up performance can be achieved in case the ST is controlled as a unique and full-interconnected system with the balancing strategy performed into the isolation stage [10]. This approach can avoid the risk of overvoltages or/and overcurrents in the CHB converter. The DAB converters, with integrated voltage balance controllers, start before the CHB converter, and as a consequence, balanced voltages of the dc-links in the MV side are achieved.

B. Soft-Charging of the DC-Link Capacitor in the LV Side
The precharging of the dc-link capacitor in the LV side is necessary as initial condition to start the control of the DAB converters while an energized MV dc-link is connected to the input port of the dc/dc isolation stage. Indeed, at the DAB converters start-up, the uncharged capacitors would act as virtual short circuits allowing a fast increase of the current over the rated and safe operating conditions. At this stage, the DABs starting current is not determined by the controlled phase-shift angle between the voltages at the primary and secondary sides of the HFT, but it is only determined by the electrical circuit parameters. Hence, the HFT peak current value is directly proportional to the equivalent input voltage.
Referring to the power stage parameters reported in Table I  (see Section II   current limitation in the DAB converters start-up. In this article, it is hereby extended to the ST application.

C. Overall ST Start-Up Scheme
The overall scheme of the proposed ST start-up procedure is shown in Fig. 4(a). At first, the MV dc-link capacitors are charged with the CHB acting as a passive rectifier; later, the LV dc-link capacitor is charged through a modified modulation technique applied just to the primary H-bridge of each DAB converter; successively, the DAB converters are activated controlling both the LV dc-link voltage and the balance of the MV dc-links. Finally, the CHB is activated to control the overall MV dc-link. In Fig. 4(b), a timeline with the indicative duration of each step of the proposed start-up procedure is shown. The first two steps are the most time consuming due to the MV and LV dc-link capacitor precharging. Instead, the duration of the remaining steps mostly depends on the control bandwidth designed in each control loop.

III. ST MODELING AND BALANCE CONTROL
The design of the start-up procedure depends on the ST power stages topologies, their control systems, and the operation modes. However, the ST can be controlled and soft-started as a unique converter.
In this case, the small signal model of the ST as a full interconnected system is fundamental in order to tailor the control system design and to carry out a tuning procedure, taking into account voltages imbalance condition.
The model of the first two stages of the ST can be derived, as in [10], referring to Fig. 5. The ith cell small signal model of the CHB is represented by the following equations: where L g and R g represent the grid impedance parameters, E is the grid voltage,Ī g is the rated grid current amplitude,M is the rated modulating signal amplitude, N is the number of CHB cells, C i is the ith MV capacitance,V DC,i is the ith MV dc-link nominal value, and d i is the duty-cycle of the ith CHB cell. The DAB converters are modeled in the input and output sides as current sources [10], denoting the input current with I DC,i and the output current as I o,i . The DAB small signal model is represented by the following equations: where V o is the LV dc output voltage, ϕ i is the phase shift of the ith DAB and T DAB is the DAB switching period, L k is the equivalent inductance of the HFT, n is the HFT turn ratio, andφ is the steady-state DAB phase shift angle between the voltages at the primary and secondary sides of the HFT. Assuming that the outputs of the DAB converters are parallel connected, the resulting output voltage is where R o and C o are, respectively, the equivalent LV dc output resistance and capacitance, and N is the number of parallel DAB converters. In order to decouple the output voltage from the variations of each dc-link voltage, an additional term can be added to the phase shift of each DAB converter, as shown in Fig. 6. The gray branch in Fig. 6 contributes to the output voltage control, thus it can be neglected in the balancing transfer function between the ith DAB phase shift and the ith dc-link voltagẽ Substituting (7) in (3), the DAB converter current can be expressed asĨ The last term in (8) can be compensated modifying the dutycycle of the ith CHB cell as In case of perfect compensation, the entire system can be described by a new set of equations as follows: Substituting (10) and (6) in (11), it results Limiting the analysis to the effects of the phase shift variation on the voltage balance, the term with I g,i in (12) can be neglected. Substituting (15) in (12), it results iñ Choosing a PI for the balance control (see Fig. 7), it results where K BAL,i denotes the proportional gain and K I,i denotes the integral gain. The integral gain can be set in order to delete the slowest pole, hence it can be defined as with N(s) and D(s) defined as

D(s)
Denoting the following constant gains as The open-loop transfer function becomes (23) Considering an ST based on a five-level CHB converter and two DAB converters with the power stage parameters defined in Table I, the Bode diagram of the voltage balance transfer function G BAL is represented in Fig. 8. Neglecting the small deviation in the low-frequency area, it can be approximated to the Bode diagram of an integrator with gain equal to K sys . The computational delay is taken into account with a first-order transfer function whose time constant is equal to the switching period of the DAB T DAB.
As defined in (22), the gain of the system is proportionally dependent on the value of K BAL . The Bode diagram of the voltage balance loop transfer function G BAL is shown for different values of K BAL in order to provide a tuning guide line, based on the desired bandwidth. Looking at Fig. 8, the bandwidth of the voltage balance loop (about 50 Hz) is chosen in order to be about ten times smaller than the bandwidth of the output voltage control loop. In conclusion, the small-signal model of the ST is required for the tuning of the voltage balancing controller achieving decoupling between the output voltage control loop and the voltage balancing control loop.
Considering the tuning strategy presented in [10] and the controller parameters in Table I,  case of 10-ms settling time. It can be observed that the controller parameters are chosen in order to guarantee that the output voltage control loop is at least ten times faster than the CHB voltage control loop. Second, at t = 1.1 s, the input voltage V DC has been imposed as output voltage reference (V * o = V DC ) and a ramp voltage with a slop of 80 V/80 ms (1 kV/s) is set as reference. Hence, the voltage reference rises from 170 to 250 V in order to emulate the start-up procedure. The results prove tracking capability with settling time of 120 ms and negligible overshoot (around 0.2 V). Instant power transfer between the MV and LV dc-links matches limited peak current in the DABs HFTs. The peak current in the HFT depends on the difference between the input and output voltages.

IV. ST: SOFT-START PROCEDURE
The proposed soft-start procedure deals with the three-stage ST whose model and control systems are analyzed in Section II. It consists of four steps described in the following and providing as advantages: balanced dc-link voltages in the ST MV side and inrush current limitation.

A. First Step
The first step consists in the connection of the CHB converter to the main grid. The system is charged through a precharging resistor connected between the grid and the ac side of the ac/dc converter in order to avoid a large inrush current. The resistor is then by-passed meanwhile passive rectifier operation is perpetuated by the antiparallel freewheeling diodes of the CHB converter to charge the MV dc-link capacitors. In this condition, no loads are connected to the dc-links in the MV side. The power drained from the main grid is limited to the amount required to supply the MV dc-link capacitors C i , internal series resistance R s,i , and the parallel resistance R p,i . The parallel resistances do not absorb significant power compared to the rated power of the ST since R p,i are in the kΩ range. In Fig. 10, the components involved in the current path are marked in black, whereas the devices in gray are turned OFF. Due to the mismatch of the capacitances and resistances parameters (see Table I), the steady-state voltage values in the dc-links are different: V DC,1 ࣔ V DC,2 . At no load operation, the effect of the parameters mismatch is amplified and the voltages are significantly unbalanced.

B. Second Step
The aim of the next steps is to overcome the voltage imbalance, which results from the first step, through a balancing procedure operated by the DAB converters. A similar approach has been proposed in [19] avoiding the occurrence of overcurrent during the turn-ON of the DAB converters and in case of no precharging of the output capacitor C o,i .
The phase-shift angle between the primary and secondary voltages of the HFT cannot be used to reduce the inrush current. Differently, the maximum inrush current can be adequately reduced by controlling the zero-voltage state in the leading bridge of the DAB. In this article, the zero-voltage state is obtained applying an independent switching law to the two legs of the same H-bridge. In particular, the zero-voltage state is achieved shifting the carrier of the leg B with respect to the carrier of the leg A. In such way, when in a switching period T DAB , both S 1 and S 3 are turned ON or OFF, the voltage in the primary side of the HFT is zero.
In Fig. 11, the switching signals, related to the first bridge of the DAB converter, are represented in four different shift cases with the related primary and secondary voltages and the current in the HFT. For each DAB, when the first bridge of the DAB is turned ON, the second bridge is kept OFF. The switches in the primary side are driven as in Fig. 11, varying the time shift  from zero to T DAB /2 with a ramp signal. This modulation can be denoted as DAB soft-shift start modulation (SSSM).
Due to the discontinuous conduction mode (DCM), the current through the transformer leakage inductance appears limited avoiding the burnout of the IGBTs. During this second step, the second bridge of the DAB operates as a diode rectifier (see Fig. 12). The transferred power precharges the output capacitor up to a voltage value, which depends on the input voltage value, voltage drops across the semiconductors devices, and transformer internal resistance.
The precharging voltage induces current circulation into the load and a certain amount of power flows from the grid to the dc load. The CHB converter in the second step still operates as a passive rectifier, and as a consequence, the grid current is highly distorted. The grid current increases slowly and it avoids overcurrent also in the CHB converter. Also the output voltage and leakage inductance current increase slowly. The velocity of the precharging procedure depends on the slope of the ramp used to increase the time shift between the two carrier signals of the first H-bridge in each DAB converter. The second result of this step is the convergence of the dc-link voltages to a new   steady-state point characterized by a smaller voltage imbalance than the previous state (see Fig. 13 at t 1 = 0.4 s where the system is in no-load operation and R o is connected but not energized).
Considering the power stage parameters reported in Table I (with R o = 32 Ω), the voltages and current waveforms are shown in Figs. 13 and 14 in the time interval between t 2 = 0.5 s and t 3 = 1 s. The new reached steady-state leads to the next step. In Fig. 15, the HFT primary-side currents during the soft-start procedure are shown. Considering the IGBTs module rating (see Table I), the current in each DAB is inside the safe operating area.

B.1) Soft-Switching of the DAB Soft-Charging Procedure:
Soft-switching operation is verified in the primary H-bridge of each DAB during the LV soft-charging procedure. The softswitching analysis is provided for the primary-side H-bridge since the secondary side is not controlled (diode rectifier). To analyze the soft-switching capability, the typical DAB HFT voltages, current, and gate driver signals during the soft-charging in discontinuous conduction mode are shown in Fig. 16.
Here, V P , V S , and i DAB indicate the primary and secondary side voltages and the current in the DAB HFT, respectively. ZCS and ZVS indicate zero-current and zero-voltage soft-switching conditions. From Fig. 16, it can be seen that ZCS occurs at the turn-OFF of S 2 and consequently at the turn-ON of S 1 , due to the zero current shown at the switching condition.
On the other way around, ZCS occurs at the turn-OFF of S 1 and consequently at the turn-ON of S 2 . Analyzing S 3 and S 4 , ZVS occurs at the turn-ON in both S 3 and S 4 , whereas hard-switching occurs at the turning-OFF in both S 3 and S 4 . Soft-switching is verified in the following cases: S 1 and S 2 have ZCS at turn-ON/OFF, S 2 and S 4 have ZVS at turn-ON.

B.2) Design of the Ramp Slope-Rate for the DAB Soft-Start:
The design of the ramp slope-rate used in the DAB soft-start procedure is based on mathematical calculation of the DAB HFT current peak.
Looking at Fig. 16, (DT DAB )/2 denotes the generic time-shift as a function of the duty-cycle D (with 0 ≤ D ≤1). In a switching period T DAB , (DT DAB )/2 represents the time duration of the positive and negative voltage related to the overall V P waveform, respectively.
Considering a constantly energized MV dc-link with V DC,i as input voltage and assuming the output voltage V o constant for a period, the current in the DAB HFT increases with a fixed rate. In a switching period, the current peak value related to the primary-side HFT is Thus, (24) gives evidence that the peak value of the HFT current in the primary side depends on the difference between the MV and LV dc-side voltage, and it depends on the value of the duty-cycle in that period. The switches in the primary side are driven varying the time shift (DT DAB )/2 from zero to T DAB /2 with a ramp signal or, equivalently, varying the dutycycle from zero to 1. As a result, the output voltage V o rises up to the steady-state value with a trend that can be reasonably approximated to a linear function as follows: where r d (s −1 ) and r o (V/s) are the slope-rate of the duty-cycle D and of the output voltage V o , respectively. By substituting (25) in (24), the resulting function, which represents the time evolution of the HFT current peak during the soft-charging process, can be expressed by where (26) represents the equation of a parabola, whereas I DAB,pk is the maximum value assumed by the peak current during the soft-charging process. More generically, (26) can be written as (28) where it is highlighted that the output voltage slope-rate is a function of the duty-cycle slope-rate.
Equations (26)-(28) are validated by simulation results conducted during the soft charging for different values of r d , as shown in Fig. 17. The parameters can be derived from Table I, when light-load condition is applied and V DC,i = 250 V. Similar results would be found in case of soft charging at rated load condition, but they are not included in this article.
Simulation results show that each current in the primary side of HFT is enveloped by the parabolic current, as obtained Fig. 18. HFT inrush current peak estimated by (26) or (28) for several dutycycle slope-rates r d and input voltages V DC,i , at light-load operation. Fig. 19. HFT inrush current peaks as function of the duty-cycle slope-rate for several input voltages V DC,i , at light-load operation. by (28). Furthermore, the maximum inrush current peak I DAB,pk calculated by (27) matches exactly with the peak value provided by the simulation.
Differently in Fig. 18, there are reported the values of the HFT inrush current peaks for different values of the duty-cycle slope-rate r d and for different values of the input voltage V DC,i . The results show that the higher is r d , the faster is the charging process, at the expense of higher HFT inrush current peaks.
Furthermore, Fig. 18 demonstrates that it is possible to accelerate the charging process duration in low input voltage V DC,i condition. As a consequence, the DAB can be soft-started and controlled ensuring high performance operation also before the CHB MV dc-link reaches the rated voltage value.
In conclusions, the duty-cycle slope can be derived from the previous equations and/or from graphical representation, as shown in Figs. 18 and 19, considering the power modules maximum peak current, the input voltage V DC,i , and the start-up time constraint.

C. Third Step
Due to the voltage drop across the devices of the first H-bridge, across the HFT and across the freewheeling diodes of the second H-bridges, the DAB converters output voltage value is lower than the input rectified voltage. In order to compensate this voltage drop, a proper control action of the output voltage is required. Turning on the switches in the second DAB H-bridge and adjusting properly the value of ϕ i (phase shift control variable), the control of V o can be achieved. Hence, the reference is varied up to V * o , which can be set as At the same time, the voltage balance control is also turned ON. The balancing is performed by the DAB converters adjusting properly the phase shift ϕ i . At the end of the third step, the following conditions are verified: the dc-link voltages are perfectly balanced by the DAB balance controllers and the output voltage V o is controlled through a PI controller (control scheme of Fig. 6). This third step is summarized in Figs. 13-15 in the time interval between t 3 = 1 s and t 4 = 1.2 s.

D. Fourth Step
In this stage, the CHB converter switches from passive rectifier to active rectifier operation and the total MV voltage control can be achieved. The parameters of the CHB voltage controller are set in order to achieve a tradeoff between fast dynamics and low overshoot (see Fig. 13).
The DABs controller parameters are tuned in order to guarantee dynamic performance around ten times faster than the CHB voltage controller [10]. The CHB control parameters are reported in Table I.
At the beginning of the fourth step, the output voltage reference V * o is set as in (29) and the secondary bridges behave similarly to the primary bridges for each DAB converter. The voltage balance is verified during all the transient behavior and dangerous overvoltages and/or over currents are avoided. Since the DAB controller exhibits fast dynamic performance and full voltage control, the dc/dc isolation stage guarantees fast power transfer between the MV and LV ac side. When the nominal steady-state MV dc-link voltage is reached, the output voltage reference V * o is set to its nominal value. The MV dc-link voltages and the grid current are represented in Fig. 13 in the time interval between t 4 = 1.2 s and t 5 = 1.8 s. The output voltage V o is represented in Fig. 14.

E. Fifth Step
The proposed ST is based on a three-stage architecture; however, the focus of this article is on the start-up of the first two stages. As in [10], the proposed architecture is conceived to be coupled with dc smart grids. For this reason, it has to be considered also the event that the LV dc-link is directly connected to dc loads, sources, or distribution bus. In order to avoid loss of generality, some hints about the start-up procedure of the dc/ac converter in an ST-fed grid are given here.
The LV-side converter is in charge of forming the grid. The main requirement to take into account during the first grid energization is the necessity to avoid instabilities, which can arise in several points of the grid due to different loads properties  and configurations. In [8], an innovative procedure based on online grid identification and lead-element filtering is proposed to energize the grid and to connect step by step each loads when stable grid condition is verified.
During the ST-fed grid startup, the power is first used to energize feeders with a majority of passive loads. The ST LV-side voltage will not reach the nominal value but a low value so that all the grid-converter-based DERs cannot connect to the grid. The grid voltage will increase gradually to the nominal value meanwhile the online grid impedance identification provides initial parameters to an adaptive stabilizing filter. Distributed sources and active loads including grid-converter-based DERs will connect to the grid when it is stable.

F. Soft-Start Procedure at Light-Load Operation
The proposed start-up procedure is applied in a different power condition and, in particular, when light-load operation persists during all the soft-start period. This condition is emulated in the model of the overall system with an output load R o of 10 kΩ. Figs. 20 and 21 show the dc-link voltages, the grid current, and the output voltage during the soft-start procedure at light-load operation. In the first step condition, the same voltage imbalance of the previous case is verified. Differently, when light-load condition is verified throughout all the start-up phases, In the start-up procedure described earlier, the second step aims to the DAB converters inrush current limitation. During light-load operation, even small parameters mismatch between different power cells leads to great imbalance condition in the MV dc-link voltages, and consequently to unbalanced inrush current in each DAB converter.
The maximum inrush current can be equally shared by the DAB converters changing properly the slope of the soft-shift start ramp of each converter, as shown in Fig. 22. Since the ramp slope depends on the difference between the input and output voltages, less slope corresponds to higher voltage difference. In Fig. 22, the DABs input voltage V DC,i , the HFT primary-side current i DAB,i , and the output voltage V o are also shown. In the same figure, a zoom-in in the HFT currents highlights the capability to share and to limit equally the maximum inrush current in both the DAB converters. The

V. EXPERIMENTAL RESULTS
In order to validate the proposed soft-start procedure, a small scale ST prototype has been developed and shown in Fig. 23. It consists of a five-level CHB active rectifier connected to the grid and DABs connected to each of the MV dc-links. For a proof of concept, the small scale ST prototype has been connected to a 230 V/50 Hz ac grid and each cell of the CHB converter contributes with 250 V and the overall MV dc-link voltage is 500 V. Without loss of generality, the acronym MV dc-link is here used referring to the dc-link connected to higher voltage side of the ST.
The DABs are parallel output connected and they feed a 2-kW resistive load. All H-bridges, the CHB converter and the DABs have been assembled with the same IGBT Danfoss module DP25H1200T101616 and the system is controlled with a dSPACE SCALEXIO system based on three DS2655 FPGA base boards; each board has been programmed with a FPGA Xilinx blockset toolbox. Each step of the start-up procedure has been experimentally proven and analyzed in detail. Looking at Fig. 23, the ST setup is depicted during control test in case of steady-state operation and unitary power factor operation.
In Fig. 24, the MV dc-links voltages (V DC,1 , V DC,2 ) and the grid current during the initial charge of the capacitors through the inrush resistor in the MV ac side are represented. The system is charged through a precharging resistor and the inrush peak current is minimized to a value of 6A peak .
In Fig. 25, the same quantities shown before are represented during the entire procedure period, with a zoom during the operation from passive to active rectifier. At the beginning of Fig. 25, the first step operation can be recognized; indeed, the ST is connected to the grid as a pure rectifier and, due to the parameter mismatches between the cells, the steady-state voltages reached in the MV dc-links are different.
The second step is represented by the precharging of the output voltage capacitors through the use of the DAB converters soft-shift start modulation. The second step results in convergence of V DC,1 and V DC,2 to a new steady-state point  and it produces an increment of the absorbed grid current. In this new load condition, the parameter mismatch between the power modules corresponds with smaller voltage imbalance in comparison with previous step where the system was in no-load operation (R o connected but not energized). The duration of the precharging depends on the DABs and the HFT rated current.
The duration of the precharging can be adjusted varying the slope of the ramp used to increase the time shift in the switching commands of the DAB legs.
In Fig. 26, the output voltage V o during the entire procedure period is represented with particular focus to the precharging phase. During this phase, the output voltage rises with an overdumped transient behavior similarly to a first-order system and with an estimated duration of T settling = 1 s. It represents a good tradeoff between overcurrents avoidance and a fast soft-start operation.
In Fig. 27, the primary and secondary side voltages of the HFT are represented together with the HFT primary-side current for three different values of the time shift during the soft-shift start precharging operation of the output voltage.
The fourth step is represented in Fig. 25 with a zoom during the transition from passive to active rectifier operation of the CHB converter. In this step, the full control of the overall MV  The output voltage reference is set to be equal to the instantaneous average value of the measured MV dc-link voltages, as in (29). Due to the high bandwidth of the DAB converters control, it is possible for the dc/dc isolation stage to track and balance instantly the input MV dc-link voltages. Hence, the DAB converters provide a fast power link transfer between the MV and LV ac side. The output voltage V o during the third and the last stage is represented in Fig. 28. Remarkably, the experimental results fit the simulation results shown in Figs. 13 and 14, during all the soft-start operations and it proves the validity of the proposed structure.

VI. CONCLUSION
In this article, a novel soft-start procedure designed for a three-stage ST based on CHB and DAB converters, which is controlled as a unique converter, is proposed. During the first steps of the start-up, the CHB converter operates as a passive rectifier while the dc/dc power conversion stage adjusts the dc-links capacitors voltages progressively to the reference value. The proposed SSSM modulation applied to the DAB converters allows to limit the inrush current avoiding overcurrent overshoots without the use of any APU. The adopted voltage control strategy ensures voltage balancing in every operation condition. Experimental results confirm the excellent performance of the proposed start-up procedure.
Final remarks are summarized in Table II, where the proposed start-up procedure is compared with the state of the art in terms of MV dc-link balancing capability, parameter mismatch tolerance, inrush current controllability in each dc/dc converters, start-up dynamic analysis, and absence of APUs.