Design optimization on conductor placement in the slot of permanent magnet machines to restrict turn-turn short-circuit fault current

Arumugam, Puvaneswaran (2016) Design optimization on conductor placement in the slot of permanent magnet machines to restrict turn-turn short-circuit fault current. IEEE Transactions on Magnetics, 52 (5). ISSN 0018-9464

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Abstract

In Permanent Magnet (PM) machines, a turn-turn Short-Circuit (SC) fault is the most critical fault to eradicate. The fault introduces high SC current in the shorted turn which may consequently lead to secondary faults unless the fault is appropriately controlled. This paper proposes feasible conductors’ placement in a slot of PM machine to minimize such turn-turn fault current. In order to minimize the fault current, the conductor arrangement in a slot is optimized using multi-objective Genetic Algorithm (GA) incorporating with both analytical and Finite Element (FE) numerical tool. The possible combinations of conductors’ placement are set as variables and optimized for a given machine which is designed for safety critical applications. It is shown that the fault current associated to a single turn fault can be significant for the random winding placement even though the remedial strategies are put in place. It is also shown that the fault current can be limited significantly by rearranging the winding placement in a way to share slot-leakage fluxes. This is confirmed via experiment on E-core. Influences of the winding arrangement on both frequency dependent resistances and windings capacitances are experimented. It is demonstrated that adopting the winding arrangement that shares the slot-leakage flux effectively benefits to minimize the AC losses in addition to improved fault tolerance. But it increases the turn-turn capacitances whose effect however can be neglected as the resonance frequency occurs beyond the operational frequency range of the machines of interest

Item Type: Article
Additional Information: ©2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.
Keywords: Electric, Fault Tolerance, Genetic Algorithm, Mitigation, Optimization, Permanent magnet, Reliability, Short-Circuit
Schools/Departments: University of Nottingham UK Campus > Faculty of Engineering > Department of Electrical and Electronic Engineering
Identification Number: https://doi.org/10.1109/TMAG.2016.2516504
Depositing User: Burns, Rebecca
Date Deposited: 30 Aug 2016 14:12
Last Modified: 25 Sep 2016 00:38
URI: http://eprints.nottingham.ac.uk/id/eprint/36116

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