High temperature pulsed-gate robustness testing of SiC power MOSFETs

Fayyaz, A. and Castellazzi, A. (2015) High temperature pulsed-gate robustness testing of SiC power MOSFETs. Microelectronics Reliability, 55 (9-10). pp. 1724-1728. ISSN 0026-2714

Full text not available from this repository.

Abstract

Silicon Carbide (SiC) gate oxide reliability still remains a crucial issue and is amongst the important consideration factors when it comes to the implementation of SiC MOS-based devices within industrial power electronic applications. Recent studies have emerged assessing the gate oxide reliability of SiC MOSFETs. Such studies are needed in order to fully understand the properties of SiC/SiO2 interface which is currently holding back the industry from fully utilising the superior features that SiC may offer. This paper aims to present experimental results showing the threshold voltage (VTH) and gate leakage current (IGSS) behaviour of SiC MOSFETs when subjected to pulsed-gate switching bias and drain-source bias stress at high temperature over time. The results obtained are then used to investigate the gate-oxide reliability of SiC MOSFETs. 2D TCAD static simulation results showing electric field distribution near the SiC/SiO2 interface are also presented in this paper.

Item Type: Article
RIS ID: https://nottingham-repository.worktribe.com/output/756093
Keywords: SiC; Power MOSFETs; Gate-oxide reliability; Robustness; Wide bandgap; SiC/SiO2 interface
Schools/Departments: University of Nottingham, UK > Faculty of Engineering > Department of Electrical and Electronic Engineering
Identification Number: https://doi.org/10.1016/j.microrel.2015.06.141
Depositing User: Eprints, Support
Date Deposited: 03 Aug 2016 10:16
Last Modified: 04 May 2020 17:12
URI: http://eprints.nottingham.ac.uk/id/eprint/35663

Actions (Archive Staff Only)

Edit View Edit View